Synopsys, Inc. announced the silicon proof of DesignWare® 112G Ethernet PHY IP in 5nm FinFET process, delivering significant performance, power and area advantages. The area-efficient DesignWare 112G Ethernet PHY enables designers to optimize highly dense system-on-chips (SoCs) with placement-aware IP that maximizes bandwidth per die-edge through stacking and placement on all four edges of the die. To extend performance, the DesignWare 112G PHY demonstrates zero bit-error rate post forward-error correction in greater than 40dB channels while offering power-efficiency of less than five picojoules per bit (pJ/bit).  Combined with Synopsys' routing feasibility study, packages substrate guidelines, signal and power integrity models, and thorough crosstalk analysis, Synopsys provides a comprehensive 112G Ethernet PHY solution for fast, reliable SoC integration. DesignWare 112G Ethernet PHY is an integral part of Synopsys' comprehensive IP portfolio for high-performance cloud computing applications, including widely used protocols such as PCI Express®, DDR, HBM, Die-to-Die, CXL and CCIX. DesignWare IP: Synopsys is a provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare IP portfolio includes logic libraries, embedded memories, embedded test, analog IP, wired and wireless interface IP, security IP, embedded processors, and subsystems. To accelerate prototyping, software development and integration of IP into SoCs, Synopsys' IP Accelerated initiative offers IP prototyping kits, IP software development kits, and IP subsystems. Synopsys' extensive investment in IP quality, comprehensive technical support, and robust IP development methodology enable designers to reduce integration risk and accelerate time-to-market.