Cadence Design Systems : Media Alert: Cadence to Showcase Signal Integrity Solutions for System-Level, Power-Aware Multi-Gigabit Interface Compliance at DesignCon 2016
January 13, 2016 at 09:39 pm IST
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Media Alert: Cadence to Showcase Signal Integrity Solutions for System-Level, Power-Aware Multi-Gigabit Interface Compliance at DesignCon 2016
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced plans to exhibit its latest Sigrity™ signal analysis and power integrity technologies for system-level, power-aware multi-gigabit interface compliance during this year's DesignCon at booth 515 from January 19 to 21, 2016, in Santa Clara, Calif.
Cadence also plans to demonstrate the latest multi-link and multi-protocol PHY for PCI Express® (PCIe®) 4.0 to address the requirements of the datacenter, server and storage markets. This next-generation PHY provides the flexibility of mixing networking protocols with a single macro and offers long reach and high-power efficiency for green datacenters.
To register for the conference, visit www.designcon.com/santaclara/registration.
WHAT:
The following demonstrations are scheduled for the show:
Constraint-driven power integrity design and analysis featuring decoupling capacitor (decap) placement guidance and design rule check (DRC) markers located where IR drop is not within pre-defined specifications
Power-aware memory interface design and analysis of the latest DDR and LPDDR interfaces
Multi-gigabit serial link design and analysis featuring compliance tests for PCIe, MIPI and USB
PCIe 4.0 multi-link and multi-protocol PHY to address requirements of the datacenter, server and storage markets
In addition, experts from Cadence are scheduled to deliver several speaking sessions to discuss new developments in these technologies and how they can help solve today's signal integrity challenges. The Cadence® speaking sessions planned are:
Panel: Reducing Noise in Power Distribution Networks on Time and in Budget:
Tuesday, January 19, 4:45pm - 6:00pm, Sam Chitwood, product engineer
Access to 3D Electromagnetic (EM) Simulation-For Those Who Care and Those Who Couldn't Care Less:
Wednesday, January 20, 1:45pm - 2:25pm, Brad Brim, product engineering architect
Learn How to Turn Simulation into Reality for PAM4 Analysis:
Wednesday, January 20, 2:50pm - 3:30pm, Ken Willis, product engineering director
Panel: Needs and Capabilities for Modeling of Capacitor Derating:
Wednesday, January 20, 3:45pm - 5:00pm, Sam Chitwood, product engineer and Brad Brim, product engineering architect
Novel Power Integrity (PI) Flow Driven Using Powertree for Easier Data Visualization and Automation:
Thursday, January 21, 10:15am - 10:55am, Mike Kang, senior staff engineer; Sam Chitwood, product engineer; Dennis Nagle, product engineering architect; Jingping Zhang, engineering R&D group director; and Dingru Xiao, product engineer
Block-Level Modeling-Based Power and Signal Integrity Performance Optimization of Integrated Core and Memory System: Thursday, January 21, 11:05am - 11:45am, Zhen Mu, principal engineer
Panel: Target Impedance and Rogue Waves:
Thursday, January 21, 3:45pm - 5:00pm, Brad Brim, product engineering architect
WHEN:January 19 - 21, 2016
WHERE:
Booth 515 at DesignCon 2016
Santa Clara Convention Center
5001 Great America Parkway, Santa Clara
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence® software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry. More information about the company, its products and its services is available at www.cadence.com.
Cadence Design Systems Inc. issued this content on 2016-01-13 and is solely responsible for the information contained herein. Distributed by Public, unedited and unaltered, on 2016-01-13 16:08:07 UTC
Original Document: http://feedproxy.google.com/~r/cadence/newsroom/press_releases/~3/BNWyjjKV6UI/pr.aspx
Cadence Design Systems, Inc. is No. 1 worldwide in developing and marketing design software for integrated circuits and electronic systems. Net sales break down by activity as follows:
- sale of licenses (93.8%): design software, integrated circuit verification, simulation, and performance control systems, etc. In addition, the group offers maintenance services;
- services (6.2%): consulting, training, system design and development, technical assistance, etc.
Net sales are distributed geographically as follows: the United States (41.4%), Americas (1.6%), China (16.6%), Japan (5.6%), Asia (18.8%) and Europe/Middle East/Africa (16 %).
CADENCE DESIGN SYSTEMS, INC. 
