Arteris, Inc. and Andes Technology announced their partnership to advance innovation for RISC-V based SoC designs for AI, 5G, networking, mobile, storage, AIoT and space applications. The Andes QiLai RISC-V platform is a development board with a QiLai SoC featuring the Andes? RISC-V processor IPs along with Arteris FlexNoC interconnect IP used for on-chip connectivity.

The QiLai SoC integrates the Andes 64-bit AX45MP multiprocessor (four cores in a cluster) running at 2.2 GHz and the NX27V vector processor running at 1.5 GHz, using Arteris network-on-chip (NoC) interconnect IP with subsystems for PCIe, DDR, SRAM and General Purpose IO using the AMBA AXI protocol. The supporting software includes the OpenSUSE Linux distribution, AndeSight? toolchains, AndeSoft?

software stacks and AndesAIRE? NN SDK to convert AI/ML models to executables. Arteris?

FlexNoC non-coherent NoC IP and Ncore cache-coherent NoC IP enable scalable, low latency and power-efficient on-chip communication to achieve superior performance in complex SoC designs. The technology facilitates the integration of high-performance, low-power CPU IPs, enhancing system functionality and interoperability, especially within the growing RISC-V ecosystem. This configurable and adaptable interconnect solution seamlessly interfaces with various components to mitigate risks and expedite time to market.

By connecting well-tested CPU IP blocks, system designers can leverage Arteris NoC IPs to enhance the reliability and quality of next-generation SoCs.