CEVA Inc. announced the release of the CEVA-TeakLite-4 v2 DSP architecture, further boosting the performance and lowering the power consumption of the world's most popular DSP architecture for audio/voice applications. The architectural enhancements incorporated into the CEVA-TeakLite-4 v2 include new power optimization features to the instruction set architecture (ISA) and power scaling unit (PSU) that facilitate even lower power consumption of up to 20%. For further die size optimizations, the latest architecture release enables a reduction in code size of up to 30% for key audio and voice codecs, significantly improving overall system cost.

Enhancements also include 50 new instructions, improved 64-bit data processing support, scalable data bandwidth up to 128-bit and a robust system interface that spans from low-power AHB bus to high-performance AXI bus with various master/slave configurations. The CEVA-TeakLite-4 v2 architecture framework is now deployed across the family of CEVA-TeakLite-4 cores, namely the CEVA-TL410, CEVA-TL411, CEVA-TL420 and CEVA-TL421. The latest enhancements that have introduced as part of the CEVA-TeakLite-4 v2 release provide further PPA optimization and increased performance for audio and voice applications, allowing the customers to truly differentiate any audio/voice enabled product.