Cadence Design Systems Inc. introduced a new version of its functional verification platform and methodologies, featuring a broad set of new and enhanced capabilities which double the productivity of SoC verification over the previous release. Incisive(R) 12.2 delivers 2x performance, a new Incisive Debug Analyzer product, new low-power modeling, and hundreds of additional features needed to perform effective verification of present complex intellectual property (IP) and SoCs. For IP block-to-chip verification, enhancements include: Doubled performance from the simulator engine; Improved debug capabilities with the recently introduced Incisive Debug Analyzer; Automated Register Validation App that replaces hundreds of functional tests with a single formal analysis run; Simplified coverage data analysis with the new Incisive Metrics Center feature.

At the SoC level, Incisive 12.2 has greater capacity for longer running simulations, including those incorporating low-power and mixed-signal designs. For SoC verification, enhancements include: An enhanced low-power algorithm in the simulator that delivers a 2x improvement in elaboration time. The new Incisive technology accurately models shutdown and recovery in low-power designs; An integrated digital-centric mixed-signal solution that uses real number models (RNM), resulting in simulation speed increases of over 300x using wreal or SystemVerilog-RNM types; Accelerated block and toggle coverage supported in Palladium XP.

Simulation Acceleration, reducing test time from hours to minutes. The new Incisive release integrates with Cadence(R) verification IP for SoC verification, the Cadence Virtual System Platform for system verification, and the Palladium(R) XP for acceleration which includes the ability to hot-swap between software-based simulation and hardware-based acceleration.